Loading ions through holes in the chip 6 may potentially be implemented with many holes near the array sites to allow rapid random access, but this would likely preclude the on-chip integration of electronic and photonic components necessary for scalable control and readout across an array. If ions are instead introduced into the array only at the edge to eliminate these requirements 5, a large overhead of quantum-logical-swap operations that scales poorly with array size is accrued. Refilling an array from loading zones at the array’s edge is limited by the time required to move an ion to interior sites and requires additional complexity in the trap electrode structure to transport ions throughout the array. Otherwise, fault tolerance may be compromised. The ion reloading process must also not lead to unacceptable levels of decoherence in nearby trapped-ion qubits. In addition, ions will be lost at random locations throughout the array, necessitating random-access loading at high rates. Even in cryogenic vacuum systems with single-ion lifetimes greater than tens of hours 2, arrays of ions approaching the physical qubit count required for practical fault tolerant operation 3, 4 will potentially require continuous reloading of empty sites at an average rate much greater than 1 s −1. However, arrays of many ions will require site reloading when an ion is lost due to collisions or reactions with background gas species. Trapped ions have the potential to form the basis of a large-scale quantum processor due to ion internal states’ natural isolation from environmental disturbances and to the straightforward, high-fidelity methods developed to manipulate those states 1.